1. Field of the Invention
The present invention relates to a method of polishing semiconductor wafers and apparatus therefor and, more particularly, a method of polishing semiconductor wafers and apparatus therefor suitable for a so-called planarization process to improve global surface flatness of a semiconductor wafer in the making in VLSI process.
2. Description of the Prior Art
Interconnections between components on top of a chip is increasingly demanding a larger space to occupy thereon, as the semiconductor industry further implements submicron technology. Therefore, miniaturization of patterns and usage of multi-leveled interconnections will take a more and more important role in VLSI technology. Along this trend in VLSI technology, a semiconductor wafer is required flat to close tolerances across one face thereof, where other materials are applied to form desired circuitry, that is, an interlevel dielectric film is deposited on the semiconductor wafer in preparation for further optical lithography to print miniature patterns for interconnections on the surface.
In the direction of the miniaturization the interconnections have a trend where the width of each interconnection will become narrower while the thickness is kept as it has been. Along this line of development in technology, insulator coverage on and around a wiring on a substrate grows poorer and poorer due to the structural sharpness of the recent wiring, which means a right angle to the base dielectric film or overhanging of the sides of the wiring on the substrate.
Progress in VLSI technology develops more and more stringent requirements on planarization processes. This trend accelerates application of the chemical mechanical polishing of silicon dioxide used as an interlevel dielectric film for the manufacture of VLSI chips.
Techniques presently used include glass reflow, bias sputter deposition, and a number of processes involving application of material in the liquid state by a spin process. None of these will planarize topography with a lateral dimension larger than 10 to 100 .mu.m. Phosphorous-doped silicon dioxide is frequently used in order to ensure uniform coverage of the next conducting layer. Chemical deposition methods are used to produce the silicon dioxide film across a substrate as an insulator between metal layers, for example, interconnections, as well as a final passivation over devices, and as a gettering source.
Phosphorous-doped silicon oxides such as PSG and BPSG are applied on chips in the form of a film covering minute step structures on the surface, which is followed by heat treatment at a temperature in the range of 800.degree. C. to 1100.degree. C. to get the doped silicon oxides to flow as a viscous fluid for the purpose of smoothing the rough surface of chips being manufactured.
The planarization process using the doped silicon oxide film deposition can be thus accomplished only by flowing such dielectric at high temperatures, so that when the highest allowable substrate temperature is less than the oxide flow temperature, for example, Al metallization was adopted on the surface of the substrate, said planarization process cannot apply. Recently interest has focused on chemical mechanical polishing technique for planarization in VLSI technology because this technique can flatten much wider surface features than those in the prior art.
There are a number of issues that must be addressed in the conventional chemical mechanical polishing technique. According to the technique, the polishing pad is capable of conforming with the warp and bow of a semiconductor wafer and this nature of the pad allows levelling of device steps on a substrate, but in view of the severe requirement for flatness to close tolerances for use in VLSI technology, the conventional technique is still unsatisfactory, due to the very nature of the conventional technique, which has been developing only to improve the parallelism between the opposite faces of a semiconductor wafer and thereby to achieve a flatness of close tolerances on one of the opposite faces.
The planarization process, which development is needed for VLSI technology, must serve to realize uniform stock removal of the surface region regardless of local variations of the bulk thickness of a substrate (hereinafter referred to as a semiconductor wafer or simply a wafer, W) as shown in section in the making of a semiconductor device fabrication in FIG. 4. After the planarization process is applied, the wafer comes to have the surface topography as shown in section in FIG. 6. In other words, in the new approach, the conventional chemical-mechanical polishing technique is affected by the change of the basic nature and starts as a technique where the new chemical mechanical polishing technique should remove the surface region in reference thereto of a substrate, for example, a CVD deposited dielectric film and thereby eliminate minute step-like projections together to finally achieve a planarized new surface for the next process, for example, metalization for interconnections.
The thus modified chemical mechanical polishing technique is hereinafter referred to as front referenced polishing technique.
In some proposals of the new approaches for the chemical mechanical polishing technique, which have been disclosed and claimed, for example, in Japanese first publication No. 5-69310 and others as shown in FIG. 18, step-like oxide projections on the oxide film 63 deposited across a wafer 6, as shown in FIG. 4 are tried to be eliminated together with a part of the surface region. The reference numeral 62 appearing in FIG. 4 designates interconnections directly applied on a wafer surface.
The apparatus disclosed in the above mentioned Japanese first application entitled "An apparatus for mirrorpolishing wafers" uses a flexible elastic membrane 71, by which a wafer is carried on during polishing. The membrane 71 are tight-stretched at and along the full periphery with a uniform tension applied by securing the periphery to lower round end of the wafer mounting head 72. A fluid supply source 73 is arranged on the opposite side of the membrane 71 to the wafer W to feed a pressure adjusting fluid on the wafer W.
The reference numerals 74, 75 and 76 are respectively a rotary shaft, a ring guide plate (or template) adhered to the lower surface of the elastic membrane, and a polishing turn table.
According to the publication, the elastic membrane 71, which seals the wafer mounting head 72 in the shape of a ring, should be good in flexibility, whereby a uniform distribution of polishing pressure is applied across a wafer W, so that sloping A along the wafer periphery is prevented to occur to the polished wafer. The sloping A is illustrated in FIG. 22(b). A polished wafer without the sloping A is shown schematically in section in FIG. 21(b).
The apparatus for polishing as shown in FIG. 20 comprises a wafer mounting plate 81 made of a rigid material, a mounting pad 82 secured to and across the lower surface of the plate 81, a template 83 in the shape of a ring on the pad 82, a soft polishing pad 85 on the upper surface of a polishing turntable 84, and the polishing turntable 84.
During the polishing, the stock removal rate of the surface region of a wafer W is strongly dependent on the polishing pressure applied. Accordingly, the front referenced polishing technique claims as indispensable conditions of application the uniform strength distribution of polishing pressure applied to the polished surface of a wafer as shown in FIG. 21(a) (uniformly distributed pressure) and limitation of the pressure application within the back surface area (the surface opposite to the polishing surface) of the wafer W, where the reference numeral 91 in FIG. 21(a) designates a wafer mounting plate and the reference numeral 92 indicates a polishing pad.
According to the apparatus for polishing disclosed in the above mentioned first publication, the elastic membrane 71 is made in uniform thickness and tight-stretched at and along the full periphery in uniform tension to the wafer mounting head 72. Therefore as indicated in FIG. 19, in case that the clearance H between the lower surface of the periphery portion of the elastic membrane 71 and the upper surface of the polishing turntable 76 is narrower than a value, the pressure applied in the periphery portion of a wafer grows larger than normally required as illustrated in FIG. 22(a), whereby sloping A occurs along the wafer W periphery. On the other hand, as indicated in FIG. 23(a), in the case that the clearance H is wider than the value, the pressure acting along the wafer W periphery is by far smaller than that acting in the mid portion of a wafer, so that the periphery portion of the wafer is less polished than the other and permits a raised or high spot B as indicated in FIG. 23(b). The exact adjustment of the clearance H is rather difficult to achieve in the current level of the art.
In the apparatus for polishing as shown in FIG. 20, mounting a wafer to the mounting head is simple to operate due to the structure of the wafer holder. However the surface contour of a polished wafer is adversely affected by local fluctuations of characteristics of the mounting pad 82 (such as thicknesses, elasticities and degrees of degradation in use) and uniform pressure distribution across a wafer is difficult to realize. Consequently the sloping A around the wafer periphery portion as shown in FIG. 22 (b) and the raise as shown in FIG. 23(b) therearound are the problems to be solved for the apparatus.
As described above, with the conventional apparatus for chemical mechanical polishing, there are left unsolved a problem of poor uniformity of polishing pressure distribution due to functional deficiency of the wafer mounting plate, though the apparatus had been devised with an intention to improve the polishing pressure distribution. A very long way still remains technologically to reach the surface flatness of close tolerances applicable to VLSI technology by means of the front referenced polishing technique since in addition to the above mentioned problem errors in machine assembly and poor dimensional accuracy of components are yet to be overcome in order to apply a currently available level of the front referenced polishing technique to the purpose.